Hello all,
I have to design a FPGA which is located solely in a small board (DB). The DB is connected to the main board with a connector whose schematic I have (all exhanged signals locations). I am requested to deliver a pinout of my FPGA, can someone tell me which are the constraints of this task? The only constraint I have in mind is that signals belonging to the same bus must be placed to pins that are very close (bit 0 next to bit 1 and so on). The timing of all signals is not critical since the maximum clock frequency of the signals is 78MHz and the technology used is LVTTL.
Thanks in advance for your help