Driving the FPGA output.

Hello all, I am working on a ARM development board. I am modifting its system FPGA which controls the peripherals. A signal output from the fpga is now in the high impedance stete from the fpga and is pulled up with a

10k resistor. VCC is 3.3V. Another signal is pulled down to gnd using a 4.7K resistor. is it possible to drive these signals from the FPGA. if yes what is the necessary modifications to be done in the ucf file (about the drive strength, pad type etc). i tried with LVTTL,PULLEDUP,Drive strength 12. But the value didnot changed. I working with a Xilinx VirtexE FPGA. Please advice me on this issue. Sumesh
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vssumesh
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"vssumesh" schrieb im Newsbeitrag news: snipped-for-privacy@g14g2000cwa.googlegroups.com...

yes, it is possible. you need some meaningful and useful design into FPGA. nobody else except you know what you want to implement so nobody can help with that. as long as FPGA output is not driving the value on those pins will remain controlled by those ext. pullup pulldown resistors as the FPGA pullup/down resistors are very large nominal comparing to 10Kohms.

Antti

Reply to
Antti Lukats

Antti Lukats schrieb:

I was in the same situation once: I had a board with an CPLD that should do something usefull later, but at the time of the first use the only job of the CPLD was to set the OE of a Flash to '1'. So I build a design with no inputs and a single output that was tied to '1'. Unfortunately the sanity check of the fitter told me that a design with 0 inputs was to large for the device that I had chosen ;-) So I added unused inputs to the design which were optimized away by synthesis. Lucky me, there was an input connected to a constant 0 signal (constant for that application) so I changed the CPLD into an inverted and it worked.

Kolja Sulimma

Reply to
Kolja Sulimma

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