constraints, etc

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Hello all,

I would like to know a couple of things if anyone could help or point me to
a file etc. I'm using Webpack from Xilinx, and a Spartan XC2S100 and I've
been messing around with writing simple project to get familiar with VHDL
and programming the board. I'm curious to know if I have to instantiate a
global clock buffer each time I sythesis my design, or if I simply make sure
that my clock goes to a GCK pin is that enough? Also I'm a little confused
as to what constraints are and how they might help my designs. For example
if I have a 30 MHz clock going to a GCK pin do I have to put constraints on
it or are constraints primarily used for very complex designs?

Sorry if this seems like small question, but it is somewhat confusing from
the documents that I have read, and since I haven't had any problems with
any of my projects (without using any constraints) I was not all that
worried. Now that I'm getting into bigger designs I figured that it was time
to start figuring this out.

Any and all help is greatly appreciated.



Re: constraints, etc

This is an FPGA question; I removed comp.lang.vhdl from this followup.

If you put your clock signal on a GCK pin, and ISE recognizes it as a
clock signal, the GBUF gets added automatically.  (ISE adds a GBUF to
almost everything it recognizes as a clock)

At 30 MHz, the only constraints you will (probably) need is to lock
down the pin numbers.

Typically, the 2nd constrain you add is the clock speed (the 1st being
the pinout).  Other constraints are added to help the software meet
the speed constraint.  (pre-assigning locations, that kind of stuff)

Hope that helps,

On Thu, 3 Jul 2003 22:13:22 -0400, "Jason Berringer"

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