Greetings:
I am coding various LP, BP, notch and LMS denoiser filters for a DSP target board with a 17 MIPS fixed point cpu, harvard arch, 4k code, 4k data (about 10 percent of each dedicated to the o/s). The DAC and ADC are 16 bit and fixed at 44100 Hz sample rate. In order to minimize the length of the final FIR decimating filter stage I precede it with three half-band FIR decimating stages to provide a sample rate of 5512.5 Hz to the last stage. The effective sample rate running in the last stage is half of that or
2756.25 Hz. This permits narrow BP filters such as Fc=400 Hz, 20 Hz bw at -50db in 200 coefficients (Remez equiripple). This is all working well except for the need to upsample back to 44100 Hz to output. I did linear interpolation which works OK at about 1/2 the Nyquist rate which is about 100 Hz too low for the example filter (in this instance, I need to insert 31 interpolated samples for each actual output sample). Short of eliminating some of the decimating stages and then needing vastly larger FIR filter orders, or using IIR for the final stage, what are some other options? With my available code and data spaces and total MIPS I have little headroom for other interpolation schemes or big filters. The board design is fixed and I cannot add addn'l hardware or change clocks.Thanks,
Michael