DDR SDRAM with Xilinx Virtex 2 on self designed PCB

Nov 22, 2004 3 Replies
E

Hello,



last week I started the development and design of a PCB with an FPGA (Xilinx Virtex 2) and two DDR-SDRAMs in parallel. No big deal, I thought, keeping in mind the most obvious design rules, i.e. combining the adress lines and separating the data and strobe (DQS) lines. But now I came across the many other signals there are, e.g. the clock signals, S0 and S1, CAS, RAS, WE, etc. My first idea was to also combine them for both modules. Lately I wondered if I am right with that assumption?



Regards, Elmo


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E

Hello and thanks Allan!

I just browsed through the recent thread. But let me pick up your question, anyhow: Yes, I want to be able to write to individual bytes and precharge one of the chips while I am performing a different operation on the other chip, i.e. I want one DIMM to load some data into memory and the other one to read data from the memory to any sort of interface. What are the aspects I must consider in connecting the DIMMs???

Regards, Elmo

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A

question,

aspects

Take GREAT care if parallelling them: You might end up with SI problems. (I'd opt for separate lines if you have the I/Os) And remember termination resistors/supply.... As well as matching delays.

/A

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From the P.O.V. of functionality, that depends on what you want to do. Will you need to write to individual bytes? Will you want to be able to precharge (or whatever) one of the chips while you are performing a different operation on the other chip?

Signal integrity implications of pairs of SDRAMs (DIMMs, actually) are discussed in this recent c.a.f thread:

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Regards, Allan

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