Forget the RAMs, I can't get Quartus to use the cascade chains!

I got my issues with the rams worked out and I belive I have an inferred design that will work in both Spartan 3 and ACEX chips with few changes. I am trying to compile this design in Quartus II 3.0 and need for the software to use the cascade chain to provide fast bus muxes with lots of inputs.

Right now my critical speed path (and one of the LE hogs) is a four input mux which I expect to be able to do in 2*n (where n is the data bus width) LEs. Each bus has a select signal which is gated with all the bits of that bus and then all of the buses are logically OR'd to complete the mux. This OR can be done by the cascade chain if the logic is inverted appropriately. Rather than depend on the software to invert all this for me, I coded the mux as an AND of ORs rather than the normal OR of ANDs. Instead of using the simple structure I am trying to get, it is use short cascades, but not in a regular way to minimize logic and delays.

Other than instantiation, is there a good way to "encourage" the Quartus tools to use the cascade chains in a structured way? If I instantiate the cascade backbone, how do I get that to simulate in Modelsim?

--
Rick "rickman" Collins

rick.collins@XYarius.com
 Click to see the full signature
Reply to
rickman
Loading thread data ...

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.