I'm in a digital logic class and am having a bit of a problem figuring out a problem. I'm not looking for an answer, per se, but would greatly appreciate any good advice or links that will help me understand how to piece everything together. The question calls for making a 4-to-16 line decoder from five 2-to-4 line decoders. The book we are using is terrible.
Initially that was my thinking, but I'm not sure where the fifth decoder comes into play. I neglected to mention that the problem needs to include an enable, so maybe that's where. As far as principles go, I understand what they do and that they're "chained" together, but it's the "chaining" together that has me lost.
Assuming your 2-to-4 line decoders have output enables, you should be able to cascade them. Take a look at the data sheet for the 74XX139. Connect one of the decoders to two address bits with its enable pulled low and connect its four outputs to the enables of four cascaded 2-to-4 line decoders with their address bits all connected to the other two address lines.
Think of a computer address bus with N bits (i.e. N inputs to your decoder). In a computer, the highest bits are decoded to provide chip selects to RAM, ROM, peripherals, etc. Each of these, in turn, decodes the highest of their bits to address components, memory chips, etc. Those cells in turn decode their bits to access individual memory locations, registers, etc.
At each step, the topmost X bits are decoded, and the remaining N-X bits are passed along to the next component. That component decodes Y bits, passing along N-X-Y bits to the next stage. Etc.
I actually printed out your diagram and am working from that. I have written out a truth table to produce all possible 16 minterms (D0-D15). I noticed some patterns in the truth table (specifically, how minterms D8-D15 are produced only when IN4 is high). Guess I just need to learn how to dissect the truth table better to come up with the digram :)
Thanks again for your schematic. It's a great help. I shouldn't be banging my head against the wall too much longer now ... :)
You can write the logic eqauations for each decoder output and design a circuit to implement it using ANDs, ORs and Inverters. For example:
OUT1 = !ADR1 * !ADR2 * !ADR3 * !ADR4
OUT16 = ADR1 * ADR2 * ADR3 * ADR4
If you do it this way, there are a couple of things to keep in mind. First, you can often simplify things by using DeMorgans theorm and second, that certain blocks appear over and over. One example of that is a 2-line -to- 4-line decoder. By using these as "builing-blocks" just like simple ANDs, ORs and Inverters, your circuit can further simplified by replacing some or all of it.
The next level of integration would be to consider doing this in a GAL, CPLD or FPGA using the logic equations more or less directly.
If you were using programmable logic there would likley be a teachable process to get to the results you want from the requirements (either minimizing logic gates, minimizing input-output delay or something else), but here you are given a bunch of pegs and have to figure out how to fit them into the given holes-- I don't think there is a formal method, just experience and pattern matching type intelligence.
That make sense. At the lowest level of the design hierarchy, I could use basic gates to implement, but I think our prof. just wants a diagram (similar to what John provided) abstracted at the decoder level.
All of this seems to make sense now. Thanks to all for the help... greatly appreciate it!
John put all the decoders in line vertically, in order to fit the schematic in the screen width. It would be easier to see the thought behind the design if the bottom decoder was drawn to the left of the other four, and vertically between the second and third decoders.
Peter Bennett VE7CEI
email: peterbb4 (at) interchange.ubc.ca