Could you give me an example on synthesis techniques?

Hi, I read a paper on FPGA design. It has the following statements:

"Successfully simulated programs might not work on device because synthesizer tries to optimize design and it can delete some connections which affect result. Hence a good knowledge of synthesizer is of importance in FPGA program development."

I have done some small and medium FPGA projects, but never experience surprising synthesis result as the above statement. Could you give me an example to show the XST synthesis control to turn a failure to success?

Thanks,

Reply to
fl
Loading thread data ...

That sentence muddles up a few things. I wouldn't spend too much time with the paper in question.

First, optimization is by definition not supposed to change the functionality. If it does, it means my code didn't completely capture the desired functionality. So this emphasizes the importance of writing correct code ...

What can happen is much more subtle than just "deleting connections". For example, off-chip signals are fairly sensitive to the way they are implemented (digital hazards by combinational logic), many things can go wrong if the implementation is sloppily done.

--------------------------------------- Posted through

formatting link

Reply to
mnentwig

By "optimization" they mean logic that is not used to produce an internal state signal or an output from the device can be trimmed away. There is no reason to implement logic if it has no impact on the function of the chip. This is also true of logic that has no driver on an input, but I believe you get errors when that happens.

I don't understand your question about synthesis turning a "failure to success".... That simply won't happen.

--

Rick
Reply to
rickman

Proper synchronous logic should simulate and synthesize properly. If you do post route timing, you should satisfy the timing requirements, or, you should find the speed at which your design can run.

Designs should not, for example, rely on delays. I believe that it is usual for synthesis to ignore any delays specified, but the simulation will handle them. Just don't do it, except for simulation fixtures, like generating clocks for simulation.

If logic is removed, it should give a warning message, and you should probably agree with the message.

-- glen

Reply to
glen herrmannsfeldt

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.