Fifo problem in Cyclone devices


I had implemented an interface between two processors with a dc-fifo in Cyclone device. the mechanism is P#1 (processor) writes a packet, signals the FPGA, the FPGA signals to P#2 for reading, P#2 reads the packet, signals the FPGA it finished reading. than the FPGA signals P#1 that it can writes a new packet. every packet is 64 words size. I perform a test of transmitting a known constant packet (a decreasing number). the test is fine but 1 100,000 packets is wrong. I thought it is a timing problem. but when I check in P#2 what packet was wrong, I found out that the packet is built by an INCREASING number until some point and then: decreasing number as it should be (in the appropriate place).

I figure it is connected to the FIFO implementation.....

Does someone hear about problems in Cyclone FIFO's?



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Sounds like a logic race.

I think it is a timing problem. Could be an unsynchronized empty/full flag. Check all inputs for synchronization to the system clock and run a static timing analysis.

Single clock fifos are fully synchronized. Dual clock fifos assume that you are doing any required synchronization yourself.

-- Mike Treseler

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Mike Treseler

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