I'm using quartus 4.2, and create some fifo with the mega wizard. on one side, synchronous data are writen at 27 MHz (from external pins), and on the other side, I'm reading the data with a 80 MHz clock (to my design).
The design assistant give me the following warnings :
Data bits are not synchronized when transferred between asynchronous clock domains Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in receiving clock domain
my fifos are : - without common clock between read and write side - the clocks are not synchronized - in legacy synchronous mode - perfomance are not maximized
What should I do ?