Hallo to Al
i use Virtex2pro and edk 6.3i,ise 6.3
I have a problem with the read fifo. I created the fifo with ed
wizard and its a part of IPIF. When you see the vhdl code belove write in the FIFO(4 Register depth and 32 Bit wide) 4 datas 1,3,5,7 But when i read the registers with the software, i get only datas and 7. The Datas between get not the fifo
Perhaphs had any the same problem
entity user_logic i
generi -- ADD USER GENERICS BELOW THIS LINE -------------- --USER generics added her -- ADD USER GENERICS ABOVE THIS LINE --------------
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-- Bus protocol parameters, do not add to or delet C_DWIDTH : integer := 32 C_NUM_CE : integer := 1 C_IP_INTR_NUM : integer := 1 C_RDFIFO_DWIDTH : integer := 32 C_RDFIFO_DEPTH : integer := -- DO NOT EDIT ABOVE THIS LINE -------------------- ) por -- ADD USER PORTS BELOW THIS LINE ----------------- --USER ports added her switch1 : in std_logic switch2 : in std_logic -- ADD USER PORTS ABOVE THIS LINE -----------------
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-- Bus protocol ports, do not add to or delet Bus2IP_Clk : in std_logic Bus2IP_Reset : in std_logic IP2Bus_IntrEvent : out std_logic_vector(0 to C_IP_INTR_NUM-1) Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1) Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1) Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1) Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1) IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1) IP2Bus_Ack : out std_logic IP2Bus_Retry : out std_logic IP2Bus_Error : out std_logic IP2Bus_ToutSup : out std_logic IP2RFIFO_WrReq : out std_logic IP2RFIFO_Data : out std_logic_vector(0 to C_RDFIFO_DWIDTH-1) IP2RFIFO_WrMark : out std_logic IP2RFIFO_WrRelease : out std_logic IP2RFIFO_WrRestore : out std_logic RFIFO2IP_WrAck : in std_logic RFIFO2IP_AlmostFull : in std_logic RFIFO2IP_Full : in std_logic RFIFO2IP_Vacancy : in std_logic_vector(0 to log2(C_RDFIFO_DEPTH) -- DO NOT EDIT ABOVE THIS LINE -------------------- ) end entity user_logic
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-- Architecture sectio
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architecture IMP of user_logic i
--USER signal declarations added here, as needed for user logi
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-- Signals for read/write fifo exampl --------------------------------------- type FIFO_CNTL_SM_TYPE is (IDLE, RD_REQ, WR_REQ)
signal fifo_cntl_ns : FIFO_CNTL_SM_TYPE
signal fifo_cntl_cs : FIFO_CNTL_SM_TYPE signal ip2wfifo_rdreq_cmb : std_logic signal ip2rfifo_wrreq_cmb : std_logic signal IP2RFIFO_Data_sig : std_logic_vector(0 t C_RDFIFO_DWIDTH-1):= (others => '0')
begi
--USER logic implementation added her
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-- Example code to read/write fif -- -- Note -- The example code presented here is to show you one way o operating o -- the read/write FIFOs provided by IPIF for you. There's a set o IPI -- ports dedicated to FIFOs, beginning with RFIFO2IP_* or IP2RFIFO_ o -- WFIFO2IP_* or IP2WFIFO_*. Some FIFO ports are only available whe -- certain FIFO services are present, s.t. vacancy calculation, etc -- Typically you will need to have a state machine to read data fro th -- write FIFO (in IPIF) or write data to the read FIFO (in IPIF) This cod -- snippet simply transfer the data from the write FIFO to the rea FIFO --------------------------------------- IP2RFIFO_WrMark