Experiences with SPARTAN3?

Thomas Bartzick a écrit:

I have just finished a VHDL PCI design in a Spartan3 and so far it works (tests are still in progress but tristate outputs are OK)

Hello Nicolas,

well I didn't mean, that tristates are basically a problem in SPARTAN3 but schematic-entry->to vhdl-transformation and also specialized cores make trouble!

We are using a core which has been originally written vor VIRTEX2-devices but was now tested on a SPARTAN3 on which we detected the described phenomenons.

A XILINX-engineer has told me that using library-primitives which carry tristates is a bad idea, because some primitives (and so the tristates of them) are no more supported by XILINX in SPARTAN3. Behavioural models should be used instead!

Ok, well any hints are welcome!

Bye, Thomas.

I rarely see any compiler generated warnings in a synthesizable design which does not translate to FATAL bugs and errors! It's better to show us your code for the tri-state drivers and I'm sure the answer will be easy.

Tristates can not be instantiated in Spartan 3 devices because Spartan

I belive in the past I was told that tristates were best instantiated because the tools had never been optimized for tristate synthesis. I'm not sure what that meant, but I guess they knew the end was in sight.

Wait a minute... Spartan doesn't have INTERNAL tristate buffers but all FPGA's have tristates on I/O pins. Were you trying to run internal logic as tristate? That is no longer available for Spartan 3. I/O pins should be tri-statable in any family, but using IOB primitives from another family can get you in trouble.

Right! This supports the result, we've got from my actual design. We have managed the tristates only on toplevel now and do not use any internal tristates (e.g. because of bidirectional lines) yet.

Now the connection of the pci-card to our development system works very fine!

Thanks a lot either!

Thomas.

Our experiences with Spartan-3 are good. Your issue with tristates may be a design structural problem. We don't use schematics but an issue with VHDL file structures which probably also applies to schematic. When a tristate is not in the top level you get an internal tristate inferred and a linked output pin usually adopts a hard level. Now given the lack of tristates the tools usual convert tristates to a logic mux in a family like Spartan-3. So if you want a pin tristate function try implementing it at your design top level.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.