Ive got differential signal ALE (composed from ALE_P and ALE_N) like in attached vhdl entity:
entity top is PORT( ALE_p, ALE_n : IN std_logic ); end top;
Could anybody tell me how in synplify constraint (sdc) assign differential pins to this signals for altera stratix 2 device?
Is such assignment valid for Synplify: define_attribute {ALE} altera_chip_pin_lc {{AA3 AA4}} ??? (lets assume that AA3 and AA4 are differential pair pins)
The easiest method is to change your entity declaration to be single- ended, and then assign a differential I/O standard to the input. You can assign the I/O standard in the Synplify constraint (sdc) file (but I don't recall the exact syntax), or in the Quartus assignment editor GUI, or with a Quartus Tcl command. So your entity declaration becomes:
entity top is PORT( ALE_p : IN std_logic ); end top;
Use altera_chip_pin_lc to assign the positive input pin to wherever you would like, and Quartus will automatically create and place the negative pin in the appropriate (paired) I/O slot.
For Stratix III and Cyclone III there is an alternative method if you prefer. For those devices, you can instantiate a differential primitive, and then assign the positive and negative pin to I/O locations yourself. This doesn't really provide extra flexibility vs. the above approach though, since the (+ve, -ve) I/O pairs are predefined, so once you assign either the positive or negative pin location, there is no choice as to where to put the other one.
Regards, Vaughn Betz Altera
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