EDK 6.1: User Logic

Hello, I am trying to add user logic to an EDK project. I have tried attching to both the OPB and PLB busses using the ssp0 reference designs. I have striped down the user logic portion of the reference designs to be like a RAM that I can write to /read from. I can download the design to the development board, but the data that I read back is garbage. In the MHS file for the core, I have: BEGIN plb_simple_core  PARAMETER INSTANCE = plb_simple_core_0  PARAMETER C_BASEADDR = 0xD0000000  PARAMETER C_HIGHADDR = 0xD000FFFF  PARAMETER c_mir_baseaddr = 0xD0010100  PARAMETER c_mir_highaddr = 0xD00101FF  BUS_INTERFACE SPLB = plb  PORT plb_clk = sys_clk END And in the C code I have: #define CORE_ADDR XPAR_PLB_SIMPLE_CORE_0_BASEADDR Xuint32 reg_0; // Write data to core XIo_Out32( (CORE_ADDR + 0x0000), 0x00000000); // or some other data // Read data from core reg_0 = XIo_In32((CORE_ADDR + 0x0000)); xil_printf("Data at address 0 is: %d \r\n", reg_0); Is this the correct method for reading/writing to the core? If so any idea where else my error could be? Thanks, Joe