My Design Implements a MB processor, and in XPS I use "Tool - > Export to ProjNav" to export the processor to my design as a sub module. The problem is that When I finish my c program, how to compile the program into BlockRAM? Since it is a XST flow, not a XPS flow, how to update the blockram in the bitstream?
I find the documents for tool "Data2mem", and use the command line to invoke this tool.
In my design, totally 9 brams are used, 4 for the MB, while the rests are for other usage. And the other 5 brams are initialized by coe file, so in Data2mem tool I only need to update the 4 brams.
I used the bmm file found in the XPS directory, but the data2mem tool gives warning: Not all BitLanes in ADDRESS_RANGE 'lmb_ram' have BMM location constraints. Some data for this ADDRESS_RANGE may have been lost during BIT file
And I wondering about why and whether this warnning will affect my design?
inport-export flow is deprecated.
1 create ISE project 2 add new source, select 'embedded processor' 3 change the EDK design 4 write your C application 5 close XPS 6 double click "Update bitstream with processor data'---------------
7 get some double-espresso 8 copy .BIT file to mini-SD card 9 insert the card into card slot of hydraXC 10 apply 3.3V powersteps 7-10 are optional :)
this flow just works, just do it as described in Xilinx documentation, no tricks no magic no special things.
I just verified this for both MicroBlaze and PowerPC systems, in both cases the project .bit files worked on first attempt nothing to change or fix.
Antti
full projectst for ISE as toplevel and MB or PPC as submodule will be uploaded to hydraxc suppport site shortly, there isnt any magic with them, but just to make the startup easier such example design may be useful - there are many ways to get it wrong
the BMM thing has been the most problematic all the time,
but with the latest ISE/EDK it actually works all fine, as long as you dont try to something the wrong (deprecated way) see my other comment.
Antti
I have solved my problem, the bmm hierarchy should be updated as the mb is changed to be a submodule. And at the end of every bram, a "Loc" attribute should be added to point out the location of the bram. After the two modification, I update the bit file without any warnings. And then I download the new bit file, and the changes in code take effect, which proves that this method works.
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