Help with Xilinx EDK 6.1

I am trying to generate a configuration bitstream for a small design using Xilinx's Embedded Development Kit. The design has a small PowerPC component and a small FPGA component. When I run bitgen on the FPGA component, it crashes silently without producing any error messages. I have tried doing this using the EDK GUI front-end (Xilinx Platform Studio) as well as from the command line, with the same result. Bitgen works fine if I try to compile a design that does not use the embedded PowerPC core.

Has anyone seen this before? Does anyone know how I can make bitgen tell me more about why it is unhappy? All I have is the crash log that XP generated and offers to send to Microsoft, and that is not telling me anything about what may be wrong. I have tried to search on as well as through google, but not found anything. I am a complete newbie to Xilinx tools, so right now I am completely lost.

Here is some more information about my setup:

I am using an xc2vp20-ff1152 chip mounted on a Xilinx AFX prototyping board. I am using ISE 6.1.03i and EDK 6.1.2, on Windows XP.

The EDK front-end runs bitgen with the command:

bitgen -w -f bitgen.ut system

Bitgen produces this output before crashing:

Release 6.1.03i - Bitgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.

Loading device database for application Bitgen from file "system.ncd". "system" is an NCD, version 2.38, device xc2vp20, package ff1152, speed -6 Loading device for application Bitgen from file '2vp20.nph' in environment C:/Xilinx. Opened constraints file system.pcf.

Sun Feb 22 19:28:24 2004

Here is the bitgen.ut file:

-g ConfigRate:4

-g CclkPin:PULLUP



-g DonePin:PULLUP

-g DriveDone:No

-g StartUpClk:JTAGCLK

-g DONE_cycle:4

-g GTS_cycle:5



-g ProgPin:PULLUP

-g TckPin:PULLUP

-g TdiPin:PULLUP

-g TmsPin:PULLUP

-g DonePipe:No

-g GWE_cycle:6

-g LCK_cycle:NoWait

-g Security:NONE


-g Persist:No

I would very much appreciate any pointers anyone could give me about how to diagnose my problem.

Thanks, Mahim

Reply to
Mahim Mishra
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Have you tried opening the .NCD file bitgen tries to convert in FPGA Editor? My guess is it's the underlying .NCD that is corrupt. In that case, FPGA Editor will crash if you try to open it...

John Williams described somnething like this not long ago. I too have encoutered corrupt .NCD-files from time to time, but I can't put my finger on it, i.e. I can't reproduce it or narrow down where it comes from.

Have a look at the logfiles, especially from the par stage, and see if there's anything unusual there. In my case par seems to finish without errors, bit generates a corrupt .NCD...

If you can reproduce this reliably, maybe you could open a WebCase with Xilinx. Since you're now the third person with the same problem, I'm beginning to believe it's not just me being too stupid to use the tools. :)

Sean Durkin
Fraunhofer Institute for Integrated Circuits (IIS)
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Reply to
Sean Durkin

Thanks for your reply! It seems in my case the problem is the one addressed by Xilinx Answer Record 18558 (should have looked there before wasting so much time over this):

Reply to
Mahim Mishra

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