On Sun, 23 Oct 2005 14:08:00 -0400, via , DarkPath spake thusly:
That last paragraph appears to be nonsense. Do you perhaps mean to reference inputs #3 and #4? At any rate, as your title implies, a Karnaugh map, drawn properly, should do the trick. What was the question again? Surely you did not intend for someone on the group to draw the map for you? Here's a reference on how to draw a map:
Well, that's a worthy goal, indeed.
How cleverly you make this sound like a homework problem.
Why? That sounds like a dumb feature, but a good one to add complexity to a homework problem. I'd want the underwater lights to be completely independent of the heat/circulation control, and possibly even the main power.
Once again a dumb-sounding feature. Wouldn't it be nicer to have the jet pump be on user demand, and the circulator only go on if the heater's running but not the jet pump?
I think it was Don Lancaster, before he abandoned electronic design for surplus baronage, who decided K-mapping was a waste of time because gates were cheap.
Don apparently didn't profit much from this idea, but some one did. Ironically, his name was.....Gates!
[snip]
IIRC, Don was an APPLICATIONS engineer at Motorola, NOT a DESIGNER ;-)
...Jim Thompson
-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | |
Whoa, Jim, it's not only IC designers who may be electronic design engineers! I'm an electronic design engineer who doesn't design ICs. Furthermore, many applications engineers are fully-educated skillful electronic designers, for example Bob Pease and Jim Williams, just to mention two familiar ones. It's fair to say Don Lancaster is an electronic designer, even though he doesn't design ICs. What he did at Motorola, I can't say, but many a clueless customer calls up and expects (and often gets, if they're big enough) free design work, designs that incorporate ICs, rather than design them from scratch. This is an issue Jim Williams describes in his app notes, telling of an anxious boss who wants to see the customer's design finished.
It's also a good exercise for IC houses, because it's a good way to learn of new IC requirements (e.g., an efficient piezo-transformer driver for laptop screen lighting), that may bring in the big bucks.
I wants to convert my old hot tub controller, wich is currently using relays, to more reliable TTL gates (solid state) and opto-isolators. Design and build a logic circuit thatl will replace the control function of the relay controller. The all solid-state circuitry would have to operate the following functions:
Switch Input #1-Main Power Switch Input #2-Underwater Light Switch Input #3-Circulator Pump Switch Input #4-Jet Pump Switch Input #5-Heat Demand Signal (thermostat)
Nothing may operate until switch #1 is activated (main power).
The light swithch (#2)may then be switched on or off independently after the main power switch is on. However, they may not operate at the same time. If one has been previously turned on, the other will not operate. The first motor function to occure will have priority.
If switch #5 (heat demand) is activated, water must be moving through the system, therefore if the water is stagnant, the circulator must start automatically. If the circulator or jet pump is already running when the heat demand is activated, no other function needs to take place. Please reply via usenet. My header is a spam trap
Do your own homework
Back in the '60's Analog chip designs were done around an application requirement. Then the applications (aka publications) group wrote it up all "purty" and nice... 'cept they often made mistakes. Some of the PLL notes are truly hilarious.
...Jim Thompson
It got so bad that we designers were spending so much time proofing data sheets that we went back to doing them ourselves.
...Jim Thompson
I've never used a K-map. They always seemed silly to me; I like logic that has intermediate terms that mean something.
Besides, you can do most logic by inspection.
And besides, FPGA compilers reduce the logic for you.
Take the current example: the correct solution to the problem isn't a K-map, it a statement that the proposed logic is stupid.
John
Ah, so his motive was to *sell* gates, rather than *use* them. I never met anyone (outside a sales, perhaps) who believed that more packages were better.
This is readily achieved by using main power to power the other logic circuitry. Must be a homework problem.
What is the antecedent to "they?" It is not clear to me at all. Did the professor post the assignment on-line? If so, it would be nice to include a URL to the assignment.
Is this supposed to be a state machine or do you just want combinatorial logic? You might ask your professor if the problem doesn't state anything about it.
--Mac
Not everyone has an FPGA compiler laying around. I can still do K-maps by hand, but I usually use...
KarnaughMap Version 4.4.5 by Russell Sasamori, which can handle up to
5 variables.BTW, gates aren't cheap, they consume _significant_ power at high speeds, and some of us fret over that ;-)
...Jim Thompson
Most of the logic we do these days is inside FPGAs, and most of that, by cell count, is data paths. And the logic is LUT-based, so pure K-map reduction isn't necessarily optimum. Logic in 22V10-type chips has its own constraints, like sum-of-products, so that's not classicly K-mappable either. And we usually tune for speed, not minimum number of gates.
Professors like K-maps because they're rigid, easy to teach and easy to test on.
The sum-of-products thing is a nice way to clearly document what's really going on. One-hot state machines are nice, too. Neither is a "classic" technique, where minimizing gates was the goal.
John
In my situation I'm building my own gates and flops from transistors. But usually trivial stuff ancillary to analog functions.
...Jim Thompson
I like them because they're easy to understand, friendly to comment, usually are bug-free, and keep fanout down, which helps speed. It's easy to duplicate state flops off-to-the-side (two-hot design?) to reduce fanout with no speed penalty. I should note that I do most logic design as schematics and pretty much expect the FPGA software to plop down a flipflop where I tell it to.
I don't mind trusting a compiler to reduce combinatorial logic for me, but I still design the logic with the FPGA cell architecture in the back of my head, so I pretty much know what's going to happen and how deep the logic will have to be.
John
Curious, why do you like one-hots? I agree that they're generally preferable with FPGA state machines but explicitly coding them seems to go against the grain. I always use enumerated types for state variables and either let the software decide on the encoding or override it (if software chooses poorly) with an attribute.
Again. one-hots are generally better in FPGAs, but "binary" or "gray" encodings are sometimes better. Since I use VHDL for control logic (I would prefer to use schematics for data-flow, but haven't mixed them) the encoding isn't really all that important to
*me*. VHDL pretty well documents the state transitions.State transition logic is no more than combinatorial logic. ;-)
Sure, I do the same, though in VHDL. Since synthesizers use templates, I know pretty much what logic is going to come out of what VHDL coding style. Of course there are FPGA-specific features (e.g. fast-carry chains) that may not drop out of behavioral style code and structural coding is needed for maximum speed. This sort of thing also limits portability, which is important to some.
If the power switch #1 is off do you have another source of power to run the logic?
DarkPath wrote: [snip garbage]
Try this logic:
ENGINEERING= HARD_WORK AND APTITUDE
DARKPATH= NOT HARD_WORKER AND NOT APTITUDE
ACTION=DARKPATH_GO_DO_SOMETHING_ELSE
Have something to add? Share your thoughts — no account required.
Ask the community — no account required