Hello,
I still try to configure a Dual Port RAM (Xilinx Spartan-IIE) I use the CoreGenerator of ISE.
I wonder, why there is a Data Out Port and a Data In Port. If I understand things right, data at the IN-port will by visible at the OUT-port (in case of configuring a port for READ/WRITE-operation).
Is it true that I have to install two ports ???? I mean - this a big amount of pins which I have to use, isn't it
16 for DIN and 16 for DOUT?But if I want to jumper DIN and DOUT I will get a problem, won't I ?? Is there a solution?
Is there someone with experiences with DPRAM's. If there is an example design - this would be very nice to get it.
Tobias Möglich