DPRAM - DIN, DOUT

Hello,

I still try to configure a Dual Port RAM (Xilinx Spartan-IIE) I use the CoreGenerator of ISE.

I wonder, why there is a Data Out Port and a Data In Port. If I understand things right, data at the IN-port will by visible at the OUT-port (in case of configuring a port for READ/WRITE-operation).

Is it true that I have to install two ports ???? I mean - this a big amount of pins which I have to use, isn't it

16 for DIN and 16 for DOUT?

But if I want to jumper DIN and DOUT I will get a problem, won't I ?? Is there a solution?

Is there someone with experiences with DPRAM's. If there is an example design - this would be very nice to get it.

Tobias Möglich

Reply to
Tobias Möglich
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Tobias, maybe this helps: The two ports are completely independent, they only share the stored data. So you can use either of both ports as write or read. (Yes, even both simultaneously as write ports!) That explains the clocking, addressing, and the Enables. If (like in a FIFO) one port is permanently Write and the other is permanently read, you just ignore (leave unconnected) the Din on the Read port, as well as the Dout on the Write port. Those data lines are of no interest in this FIFO situation. Dout on a Write port reflects the data that you are writing ( in Virtex and Spartan-II), but in Virtex-II and Spartan3 you have some interesting options: Dout can be configured to reflect the data just being written ( as in Virtex/Spartan2), or it can reflect the old data that you just wrote over, or it can remain unchanged by the write operation, just keep showing what it showed before, whatever that was. Most users ignore the Dout of the Write port; and the Din on a read port is inherently ignored by the BlockRAM. But remember, you can make any port a read or a write port, and change that assignment on any clock cycle. You are in control !

And a last rem>

Reply to
Peter Alfke

Tobias, here are the basics: ?Din is always an input, but it has meaning only for a write cycle; the read cycle just ignores the data on Din. ?Dout is always active (there is no 3-state) as either a read output, or representing the data being written ( or in V2/S3 optionally the old data or the previous data...) Interconnecting Din and Dout seems to be meaningless to me.

(Microprocessors and some memories use bidirectional data bussing mainly to reduces the pin-count. That consideration does not apply to the same extent inside an FPGA.)

Peter Alfke ==============

Tobias Möglich wrote:

Reply to
Peter Alfke

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