LFSR in xilinx 13.2

The actual LFSR description should take two or three lines, and it's not the kind of thing that needs superhuman effort to optimize, particularly if it's an internal XOR type.

An extern XOR type with a whole lot of taps might benefit from some pipelining, but even that shouldn't be too hard.

So maybe they didn't think they needed to bother.

Hi,

Here is the link to online LFSR code generator:

Thanks, Evgeni

In all ISE releases you can find example designs. XAPP211: PN Generator, is one I authored years ago. There's a verilog and VHDL version. A PN Generator is basically an LFSR. There should be enough comments in the code to explain how to infer SRL16s (vs FFs). Here're some other docs in case you're interested...

Pseudo-random Noise Generators using SRLs (app note and reference design):

HDL Coding for PN Generators:

Good luck, Mike