Hi guys,
Is it possible to somehow put a synthesis constraint (preferably with a flag or with directly in the verilog netlist and otherwise in the synthesis constraint file) such that the MUXes from the slices (e.g. MUXF5) are not used, but instead all logic is mapped directly onto the LUT's without these Muxes?
Like for example for an asic design you can tell to synopsys to not use certain standard cells by "set_dont_use { lib/gate }" I'm looking for the FPGA equivalent.
Is this uberhaupt possible? I'm using ISE 5.2 of Xilinx. The FPGA platform is the Virtex II..
Thanks,
Kris