Picky WebPACK 6.1

Hello.

I am designing a memory interface for an MCU in a SpartanII with Webpack

6.1.02i. To optimize pin usage in my design, address and data buses are muxed and I am trying to use latched addresses.

To synthetize my latch under Verilog, I first wrote.

always @(AD, A_g) if (A_g) A_r

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Pablo Bleyer Kocik
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