Timing Questions?

Dear All,

I would like to ask you some timing questions.

First scenatio and first question:

I have two signals, for example, /CS and /RD. Looking at the device datasheet it says that:

-tCLRL CS LOW to RD LOW 0 ns

-tRHCH RD HIGH to CS HIGH Intel mode 0ns

Then looking at the datasheet I must assert /CS before /RD and de-assert /CS after /RD. I would like to know if it is possible to Assert /CS and /RD in the same clock cycle or should I first assert /CS in a clock cycle and in the next clock cycle assert /RD. I mean, in my state machine would be ok to assert /CS and /RD in the same cycle due to "0ns" of the tCLRL and tRHCH or should I use two clock cycles?.

And second scenario and question:

RULE 2.58: During read cycles, the responding SLAVE MUST release all of D00-D31 before releasing DTACK* or BERR* to high.

In a Read Data cycle in an VME Slave when the slave places the data and asserts the signal /DTACK, waits until detects that /DS is high again (Master). Then must release the data bus and rise (de-assert) /DTACK at least "0ns" after releasing the data bus.

Could I release the Data bus and de-assert /DTACK in the same clock cycle or should I release the data bus in a clock cycle and de-assert /DTACK in the next clock cycle?.

Thanks a lot and best regards,

Javi

What are your priorities?

"0ns" means one signal has to happen before or at the same time as the other. If you change two signals on the same clock edge, you don't know which one of them might change first. So you need to do something to make sure the one you want changes first.

A clock cycle is the simple and clean way to do that. It costs a cycle. Can you afford that? If so, end of problem.

If you don't want to burn a whole cycle, then you start looking for tricks.

You can sometimes use the other edge of the clock. Now it only costs you a half-cycle. Or use a much faster clock where the state machine counts several clocks for each of the old states.

Add some routing delay on the PCB (6 inches per ns).

Clock one signal in an IOB and the other one in a CLB near the IOB so it takes a little longer to get out there.

Use lower drive on one signal. (This assumes the loading and layout are matched.)

[Don't forget to check the other edge too.]

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