I would greatly appreciate anyone pointing out errors in this hardware interface. I have studied the data sheets and I believe I have it correct. ;-)
uC = AT91RM9200 arm920 processor with SDRAM 16/32 bit interface in PQ208 package SDRAM chips = Micron (or similar) MT48LC128M4A2 - 8 MEG x 16 bits x 4 banks
Datasheets:
AT91RM9200:
MT48LC128M4A2:
Goal: I want to interface two of the 8MEG x 16 bit x 4 bank SDRAM chips to a AT91RM9200 in a 32 bit wide bus for a total of 32MEG x 32 bits.
Connections: The AT91RM9200 has a glueless SDRAM interface (hopefully). Both of the SDRAM chips will get the standard signals: CAS#, RAS#, SDWE#, SDCS#, SDCK, SDCKE, BA0, BA1 straight from the AT91RM9200 internal SDRAM controller.
In addition, since this is a 32 bit wide configuration, address pins A0 and A1 are not used as addresses but instead will be used in their alternate function as byte masks (A0 = NBS0, A1 = NBS2). The AT91RM9200 of course also has two other byte masks, NBS1 and NBS3.
The lower 16 data bits (D0-D15) will be connected to one of the SDRAM chips, along with NBS0 connected to DQML and NBS1 connected to DQMH. The upper 16 data bits (D16-D32) will be connected to the other SDRAM chip, along with NBS2 connected to DQML and NBS3 connected to DQMH.
The address connections for both SDRAM chips are A0 to A12. On each SDRAM chip, A0 to A9 will be connected to A2 to A11 on the AT91RM9200. SDRAM pin A10, a special case dealing with precharge options will be connected to a special pin on the AT91RM9200 called SDA10, which is different from the address pin A10 on the AT91RM9200 (how nice of them). The remaining two address pins A11 and A12 on each SDRAM will be connected to A13 and A14 respectively on the AT91RM9200.
This completes what I think is the correct way Atmel intended the AT91RM9200 SDRAM interface.
Correct?
Thanks so much for taking the time to look at this. This is my first time dealing with SDRAM (and arm chips too). Good learning experience. :-)
Rick