ANYONE HAS A VHDL CODE EXAMPLE FOR A PHERIPHERAL DEVICE INTERFACE TO A PC PARALLEL PORT(ECP)

I need a VHDL code example of a Peripheral interface that will communicate to a PC Parallel Port. The Mode of this Port communication is ECP. Any help will be appreciated.

Reply to
LRCR
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Ah, senior projects are due.

--
  Keith
Reply to
krw

No, This may seem to be a school senior project, but it is not. I am an analog designer trying to get into more on VHDL. The job at present is giving me an opportunity to start with the little VHDL experience I have. I would appreciate any help you can provide. The Yahoo and google search engine provide some help, but not enough on ECP mode. From your comment, "Ah, senior projects are due", it seems that this is an easy VHDL design for you. If so, can you help?

CAESAR

Reply to
LRCR

You might try starting with learning about the PC's parallel port. I liked the book "Parallel Port Complete" by Jan Axelson. You can get it at amazon.com . You can also look at some of the beginning VHDL books they have. Xilinx and Altera both have pretty reasonably priced development kits that you can use to get your feet wet.

Jim

Reply to
James Beck

On Wed, 24 May 2006 08:30:40 -0400, LRCR top-posted:

Well, I found a pretty good spec, but it's kind of wordy:

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And, FYI, bottom-posting is the convention here. :-)

Good Luck! Rich

Reply to
Rich Grise

Ok, it is that time of year. ;-)

deity. help us. Joerg, Jim, listening? ;-)

How about this:

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I've not interfaced to a printer in ECP mode but it looks pretty straight forward. Shouldn't be too much trouble. Sure, I think I can help. It's likely others will join the fun too.

--
  Keith
Reply to
Keith

[snip]

When I need logic more advanced than simple combinational (like a PCI bus) I hire it done ;-)

...Jim Thompson

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|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

Many thanks. I try to get the books.

Caesar

Reply to
LRCR

Thanks for the help. I'll give this website a try.

Caesar

Reply to
LRCR

Reply to
LRCR

Thanks for your feedback

Caesar

Reply to
LRCR

Are you saying that PCI is simple, or you need something more advanced than simple (example of not simple).

...besides, we do the much the same with analog trivia. ;-)

--
  Keith
Reply to
krw

If you need some help, do tell us more of the requirements. The design should be quite easy, but without requirements all you'll get is another level of crap to interface to (ECP looks trivial).

--
  Keith


> Caesar
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Reply to
krw

For the nitty-gritty on ECP mode itself (or any other parallel port mode, for that matter), you might want to check out Jan Axelson's site, LVR.COM. Seems to me she also offers RS-232 and USB tutorials. Very good stuff, all.

--
Michael
Reply to
Michael

Sure,

From reading the ECP.pdf document,the data lines is shared for both data and command (referred as data cycle or command cycle). Line HostAck is used to determine the cycle.

On the command cycle, 2 format is possible. One format is RLE and the other is address. Bit 7 is used to determined which format is selected. RLE will not be used in this application. Only the Address part is used. With 7 bits, I can used up to 128 address to select different function internal to the Altera FPGA. Also, in the command cycle, the data line will flow only in one direction(PC to my peripheral device).

On the Data cycle, both direction on the data line will be used.

There are 3 different function the FPGA will perform. Let call these function A, B, C and D.

Function A (Write Only, PC to Device)

First, the PC Parallel Port will address the FPGA for function A. Then loads via Data cycle, 2 bytes in the FPGA. The two bytes will appear on 16 pins of the FPGA. The a CS strobe is pulsed on a separate pin of the FPGA.

Function B (Write Only, PC to Device)

The PC Parallel Port will address the FPGA for function B. Then loads via Data cycle, 1 bytes into the FPGA. The 1 byte is then clocked out of the FPGA serially at 2 MHz as a SPI interface.

Function C (Write Only, PC to Device)

The PC Parallel Port will address the FPGA for function C. Then loads via Data cycle, 1 bytes into the FPGA. Each bits of this byte will control the direction of the pins of funtion D.

Function D (Write and Read, PC to Device or Device to PC)

WRITE OPERATION: The PC Parallel Port will address the FPGA for function D, Write operation. Then loads via Data cycle, 1 bytes into the FPGA. Depending on the control bits of function C, some or all of the bit of the loaded bytes will appear on up to 8 output pins of the FPGA.

READ OPERATION: The PC Parallel Port will address the FPGA for function D, READ operation. The FPGA will read the same 8 pin described above for the WRITE operation and is then transferred to the data lines of the PC Parallel Port . The PC then reads the 8 bit data.

As I see it, I will be OK with the Function part of the FPGA. But, however simple the Parallel Port is in this application, I need help on the Parallel communication protocol part. That is, how to make the data available to and from the FPGA functional part.

CAESAR

Reply to
LRCR

Good so far. Note that I've never used an Altera FPGA, so there may be differences in the implementations.

Ok, I suspected that. ;-)

Questions:

The 'CS' is strobed after the second byte appears? How long is CS?

Is handshaking on CS required?

Do the two bytes have to appear at the output at the same time or can they appear at any time before CS?

Separate output from Function A?

Addresses?

How do I know the difference between Function A and Function B?

2MHz, where? Do you have an oscillator? What frequency?

What about overruns/underruns? Frameing?

Simple enough.

Looks simple.

Direction bits? Does this read read back the bits written (and set to output) in D-Write above?

That's pretty easy. When the port is writing to the FPGA you set the FPGA drivers to 'Z'. When reading the FPGA they're driven by the input pins on your Function D-Read port. Something like:

ParallelPort 'Z');

This may have timing problems so depending on Altera's I/O you should incorporate a flipflop into the I/O cell (at least with Xilinx this works better):

PPort: PROCESS (Clock, Reset) BEGIN IF Reset = '1' THEN ParallelPort 'Z'); ELSIF Rising_edge(Clock) THEN IF FunctionD_Read = '1' THEN ParallelPort

Reply to
Keith

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