Network on chip

Hi!

Vijay wrote on 21/01/08 11:02 MET:

Do you mean something like a SOC(System On Chip) Platform with on-chip Ethernet MAC?

eg. Micrel got such SOC's witch inlude a VLAN capable Ethernet Switch on-chip:

Do you mean for on-chip inter-processor communication, or do you mean on- chip Ethernet as suggested in another thread?

I suspect that any on-chip network is either going to be very expensive in terms of silicon usage, very disappointing in terms of speed, very engineering-intensive, or very specific to your application. Unless you want to go the "very engineering-intensive" route and hope that you can sell the IP, I'd go for something simple and specific to your application.

If you don't have to implement too many connections on each block, I'd go for point-to-point links, either way-fast serial or parallel depending on which used less silicon. Alternately, a multi-master bus with either a shared memory pool or a chunk of memory that 'belongs' to each block but which is globally mapped may work quite well. If you go the 'memory belongs to each block' then you can make the memory dual port, with fast non-blocking access from the 'owner', and arbitrated access from everyone else.

Good luck (you'll need it), and have fun.

See the Sep/Oct issue of IEEE Micro, 27(5), for several chips using mesh interconnects. Tilera and Ambric appear to be commercially available.

Look at the Scalable Coherent Interface (IEEE Std 1596) for a cache coherent interconnect.

Petter

Thanks all for your replies .

I was actually referring to packet switched on chip networks . Something similar to Philips =C6thereal or Intels experimental terrascale processor architecture containing about 80 processor cores

My design is based on the ST micro Spidergon topology with wormhole routing.

Thanks again PC