Can't create Bus-Tap in Xilinx' ECS

Feb 25, 2005 1 Replies
D

Hello all,



quite embarassing question - but can't move on without the answer ...



I'm new to FPGA-programming and encountered the following problem:



suppose we have a symbol with an output pin: A(35:0) [Multiplier]



we have another symbol with an input pin: B(15:0) [Latch]



if I want to connect the two, for example A(15:0) and B(15:0), I have to extract A(15:0) from A(35:0)



HOW DO I DO THIS??



I tried to ues a bus tap, but it never worked. got the following error messages: "Error: Destination branch of bus tap at (1616 912 1712 912) is not part of the source branch of the bus tap"


it does work the other way around though, when I have a bus a(3:0) and add 4 bus taps with a(0), a(1), a(2), and a(3).


I really need help.



Thanks you in advance,



Hanns-Walter


__________________________________________ Dipl.-Ing. Hanns-Walter Schulz TU Braunschweig Institut fuer Luft- und Raumfahrtsysteme Institute of Aerospace Systems Hermann-Blenk-Str. 23 Tel.: ++49 531 391 9968 D-38108 Braunschweig Fax: ++49 531 391 9966


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J

You may need to specify what schematic input tool you're using since so much of the industry is coing HDL where all you would need to do is specify the instance port as ".B(A[15:0])" within the device instantiation.

1) Tell the folks here what schematic tool you have, 2) Consider learning Verilog or VHDL

part

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