Hi, I am getting ready to clean up some XST(Verilog) warnings, and want to open a discussion on how to eliminate/suppress unused bits coming from instantiated modules. (e.g. WARNING:Xst:646 - Signal is assigned but never used. To further clarify, say that temp is actually a [35:0] wire that connects to the output of a coregen 18x18 multiplier, but the lower 12 bits are intentionally not used. Does anybody have any Verilog type suggestions on how to eliminate the warning. I looked at ISE's 7.1 message filtering, but was wondering about reasonable alternatives?
- Newman