Tools Tree

Hi all, As there are number of point tools available in the industry for FPGA based design and implementation, it is becoming more difficult to stick to one flow. Does anybody have some sort of tools tree (2-3 tools against each node in the design flow diagram) available in the industry? This should be independent of any tool vendor but include widely used tools. I mean, I want something like this

  1. Design entry Tool1: Tool2:
  2. Synthesis Tool1: Leo Spec Tool2: Synplify Pro Tool3:...
  3. Code Coverage / Automatic test bench gen. Tool1: ... Tool2: ...
  4. Physical synthesis Tool1: ...
  5. Place and Route Tool1: ... Tool2:...
  6. STA


Thanx in advance, Nagaraj

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  1. Design entry Tool1: emacs vhdl-mode, verilog mode Tool2: Quartus block diagram
  2. Simulation Tool1: Modelsim Tool2: Aldec
  3. Synthesis Tool1: Leo Spec Tool2: Synplify Pro Tool3: Quartus Tool4: XST
  4. Place and Route Tool1: Xilinx Place & Route + static timing Tool2: Quartus Place & Route + static timing

-- Mike Treseler

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Mike Treseler

I meant much more. For a detailed design flow, including code coverage, DFT, physical synthesis, etc.

regards, nagaraj

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code coverage : tool1: v-navigator from transeda

DFT : DftAdvisor for ASIC but for fpga ????. fpga has built-in jtag boundary-scan. So you can download bsdl file for your device. altera:

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other :
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STA: tool3 : PrimeTime from synopsys

physical synthesis: what do you mean ?

regards, fe

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In the FPGA world this means applying the same synthesis techniques like register re-timing, re-structuring and re-synthesis on a place and routed design. Have a look at Mentor's Precision Physical. I suspect that RTL, Place&Route and Physical will slowly merge into 1 synthesis engine. Given the "close to useless" estimates from wireload models this can't be to soon enough :-) Hans.

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The problem with retiming in the FPGA world is not the delay model: You can do it after placement and have a really nice delay model, but the initial conditions model.

If you say "keep initial conditions/Global set-reset", its a pain in the butt and needs to be before placement.

If you say "Screw initial conditions/global set-reset" it becomes easy and nicely effective, and the designer just has to have his state machine take a startup/reset signal.

Nicholas C. Weaver                       
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Nicholas C. Weaver

Synthesis :

1.XST 2.Mentor Leo Spec 3.mentor Precision RTL
  1. Synplicity Synplify /Pro
  2. Synopsys FPGA Compiler II
  3. Synopsys Design Compiler

Physical Optimization /Synthesis:

  1. Mentor Precision Physical
  2. Synplicity Amplify
  3. Magma (acquired from Aplus) Design PALACE
  4. HDI PlanAhead

Simulation (HDL)

  1. ModelSim
  2. Cadence Verilog XL, NC-Sim
  3. Synopsys VCS

Formal Verification:

  1. Synopsys Formality
  2. Verplex (now Cadence) Conformal-FPGA


  1. Mentor Seamless


  1. Mentor Design architect
  2. Innoveda
  3. Cadence concept

Board level timing

  1. Mentor Tau

Board level Signal integrity

  1. Mentor HyperLYNX
  2. Mentor ICX
  3. Cadence Specctraquest
Reply to
Neeraj Varma

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