Greetings, I posted this in comp.cad.synthesis. That group doesn't have much traffic.
We are looking into doing a rapidchip with LSI. I would like to hear from anyone who has done a rapidchip. I'm interested in all aspects of the process with emphasis on hidden cost, "Oh you wanted timing analyses done? Well that's another 5 grand". Also how many iterations did you have to go thru with them doing the detail layout? Did they met the device delivery schedule? It looks like thier toolset does a prelimanary place and route on the customer's platform then the database is handled over to LSI for detail place and route. How long did LSI spend on detail place and toute in order to get to tape out? I understand that the time spent is dependent on the quality of the RTL, clock frequency, margin in the design, IP quality, and how many clocks. Also what was the test scan coverage obtained?
I've done ASICs in the past with LSI and found them to be real stickers for process which is good. Also we have had a quote in the past with cost associated with the distributor. Did you have to pay engineering fees to the distributor?
Also since we haven't done an ASIC in a few years here our synthesis license has expired. I am considering Amplify RapidChip physical synthesis from Synplicity. Anybody have a comment on that?
Are these question more appropriate for John Cooley's DeepChip web site? I did a search there but came up pretty empty.
Thanks in advance for any information you may share.
Regards Jerry