LSI RAPIDCHIP

Greetings, I posted this in comp.cad.synthesis. That group doesn't have much traffic.

We are looking into doing a rapidchip with LSI. I would like to hear from anyone who has done a rapidchip. I'm interested in all aspects of the process with emphasis on hidden cost, "Oh you wanted timing analyses done? Well that's another 5 grand". Also how many iterations did you have to go thru with them doing the detail layout? Did they met the device delivery schedule? It looks like thier toolset does a prelimanary place and route on the customer's platform then the database is handled over to LSI for detail place and route. How long did LSI spend on detail place and toute in order to get to tape out? I understand that the time spent is dependent on the quality of the RTL, clock frequency, margin in the design, IP quality, and how many clocks. Also what was the test scan coverage obtained?

I've done ASICs in the past with LSI and found them to be real stickers for process which is good. Also we have had a quote in the past with cost associated with the distributor. Did you have to pay engineering fees to the distributor?

Also since we haven't done an ASIC in a few years here our synthesis license has expired. I am considering Amplify RapidChip physical synthesis from Synplicity. Anybody have a comment on that?

Are these question more appropriate for John Cooley's DeepChip web site? I did a search there but came up pretty empty.

Thanks in advance for any information you may share.

Regards Jerry

Reply to
Jerry
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Hi,

The default toolchain for LSI Rapidchip is Synplify ASIC from Synplicity, If I'm correct. Perhaps, you can ask them for input. My experience with with Synplify Pro and Amplify was quite good. The only uncertainty would be the quality of the timing extraction and convergence between the tools (if separate). Time to prepare some figures (area, clocks, speed, RAM, ROM) and check with their sales representatives.

Regards, Alvin.

Reply to
Alvin Andries

Jerry - we've designed (are designing) several LSI RapidChips. Here's some comments on your posting:

- Costs are pretty out there. You need to get to a Rapid Ready Netlist using the LSI tool flow (LSI RapidWorx). Depends where you are coming from on how hard that is. If it's an FPGA design, expect to re-map the memories, re-do the I/Os, maybe change some IP, re-verify. If it's a clean design it's a case of designing for the technology.

- You'll pay; LSI NRE ($50-200K depending on chip chosen) for Netlist to chip. Synplicity tool costs ($20K or so) and that should be it. RapidWorx is free. You'll need Synopsis primetime for STA - if you haven't got it that can be pricey, or you can pay someone to do it for you on an hourly rate

- Layout is easy as long as you follow the rules - so, one iteration. The rules cover things like max speed (typically 250MHz) and getting the RTL through the design rule checker (Tera Systems, Teraform tool). The rules can be broken, but that's when physical becomes trickier and you can expect to pay some additional NRE

- Device delivery schedule.....won't lie to you here, LSI is still putting chips through a new tool flow and we've run into several gotcha's that delayed things. By now hopefully things are cleaned up (they've done about 50 chips). But don't believe their 'as easy as an FPGA' hype - it isn't. Learning the tools takes sometime.....the tools still have some bugs. Working with someone who's done it before is a huge benefit.

- Synplicity does a 'placed netlist' synthesis with pretty accurate timing.....except, one design we did had a massive fan out on the AMBA bus. We warned the end customer but he went ahead anyway. The final layout tool threw in a whole bunch of buffers and that screwed things up compared to Synplicity results. Otherwise the match has been very accurate.

- Detailed place and route time - very dependent on the size / complexity of the chip. But very fast compared to an ASIC 6-8 weeks is a good rule of thumb

- Test scan is built into the chip by LSI so you should have no worries there. You hand off RTL, they add clocks, scan chains etc. No need to worry about test coverage, signal integrity (as long as you follow the rules)

- Paying distributor - LSI uses Arrow (in North America) to deal with most customers who aren't Cisco etc. Arrow has a design center and will do most (not all) of the post Netlist engineering. So yes, you pay them. But they are highly professional and experienced. Unless you're a high volume big guy in which case you might deal direct.

and can be a real pain to work with.

Feel free to Email me with any questions or you can talk directly to one of our engineers (within reason, we have to make a living to!)

Reply to
John B

Jerry - we've designed (are designing) several LSI RapidChips. Here's some comments on your posting:

- Costs are pretty out there. You need to get to a Rapid Ready Netlist using the LSI tool flow (LSI RapidWorx). Depends where you are coming from on how hard that is. If it's an FPGA design, expect to re-map the memories, re-do the I/Os, maybe change some IP, re-verify. If it's a clean design it's a case of designing for the technology.

- You'll pay; LSI NRE ($50-200K depending on chip chosen) for Netlist to chip. Synplicity tool costs ($20K or so) and that should be it. RapidWorx is free. You'll need Synopsis primetime for STA - if you haven't got it that can be pricey, or you can pay someone to do it for you on an hourly rate

- Layout is easy as long as you follow the rules - so, one iteration. The rules cover things like max speed (typically 250MHz) and getting the RTL through the design rule checker (Tera Systems, Teraform tool). The rules can be broken, but that's when physical becomes trickier and you can expect to pay some additional NRE

- Device delivery schedule.....won't lie to you here, LSI is still putting chips through a new tool flow and we've run into several gotcha's that delayed things. By now hopefully things are cleaned up (they've done about 50 chips). But don't believe their 'as easy as an FPGA' hype - it isn't. Learning the tools takes sometime.....the tools still have some bugs. Working with someone who's done it before is a huge benefit.

- Synplicity does a 'placed netlist' synthesis with pretty accurate timing.....except, one design we did had a massive fan out on the AMBA bus. We warned the end customer but he went ahead anyway. The final layout tool threw in a whole bunch of buffers and that screwed things up compared to Synplicity results. Otherwise the match has been very accurate.

- Detailed place and route time - very dependent on the size / complexity of the chip. But very fast compared to an ASIC 6-8 weeks is a good rule of thumb

- Test scan is built into the chip by LSI so you should have no worries there. You hand off RTL, they add clocks, scan chains etc. No need to worry about test coverage, signal integrity (as long as you follow the rules)

- Paying distributor - LSI uses Arrow (in North America) to deal with most customers who aren't Cisco etc. Arrow has a design center and will do most (not all) of the post Netlist engineering. So yes, you pay them. But they are highly professional and experienced. Unless you're a high volume big guy in which case you might deal direct.

and can be a real pain to work with.

Feel free to Email me with any questions or you can talk directly to one of our engineers (within reason, we have to make a living to!)

Reply to
John B

Sorry just read through that and realised I didn't do a very good job on the flow:

1) Enter the design in LSI RapidWorx 2) Check the design in TeraSystems Teraform 3) Synthesize the design in Synplicity Amplify 4) Check STA in Synopsis primetime 5) Hand off netlist to LSI or 3rd party. John ( snipped-for-privacy@octera.com)
Reply to
John B

John, this is exactly the information I'm looking for. A user with hands on experience. I'm tending to agree with you that Arrow may earn their money since this is a new tool flow, new devices and new bugs. While I have done several ASICs in the past, the flow was toss the netlist over the fence after a few checks, run the netlist with extracted delays from place and route and maybe fix a few setup/hold problems. They always worked. With this submicron geometries with all of the second order effects the process is much more involved. Yes the NRE is high but for a full custom its even higher. I'm preaching to the choir on that.

Any idea what the hourly rate of Synopsis primetime would be? Also any idea how long it would take to do a timing analysis on 2 million gates, single clock, totally synchronous design. NO GATED CLOCKS!

LSI has a methodology that works. I hated procmon. My LSI chips always worked.

I'm somewhat surprised it takes that long for a structured ASIC. I need to understand better why it takes so long.

Another question: What is your typical gate utilization?

Again thanks for your time John.

Regards Jerry

Reply to
Jerry

I think you did a fine job.

Reply to
Jerry

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