Hello All
I'm doing a Digital DownConverter application with an overall sampling rate reduction of 640. We want to use a so called CIC or Hogenauer filter for the first decimate by 10 then follow with five decimate-by-2 halfband filters to get 640. We are using a Xilinx VirtexII XC2V6000 to implement the hardware.
We planned on using the Xilinx Coregen core for the Cascade Integrator Comb CIC filter but I am finding peculiar glitches in its output. The parameters for the filter are R=decimation=10, N=stages=4, M=difference delay=1, Bin=input width=15.
I wrote a simulation testbench that sweeps a linear FM chirp accross the entire input Nyquist range and records the output data to a file. Every 1500 output samples there is a notable glitch of magnitude -30dB with respect to the filter full scale output. I keep input amplitude less than half what the input port should be able to handle (+-8192 into 15 bit port)
Thinking that the core was bad I wrote my own CIC filter from the Hogenauer filter and it has exactly the same characteristics. With my own filter I can look at the internal integrators and differentiators and the glitches occur where there are general direction changes in the stage registers but with all that accumulator overflow going on its hard to analyze.
Has anyone else encountered this general glitching with CIC filters? Can you see a systematic way to analyze such a problem?
If interested I can share my filter design and testbench.
Regards,
Pete Dudley