1 Counter/Multiple Clocks -or- Mixing 4 Clocks To 1 Clock

Apr 19, 2005 4 Replies
B

An XOR gate will change it's output whenever an input changes. If you use an XOR gate for each pair of clocks, and feed the outputs into another XOR gate, then if any time any of the clocks change, the output will change. Thus, a counter which uses that as a clock will count the pulses.

The problem with this is that if the clock input transistions occur too close together, the input to the counter can change too quickly, and violate the setup or hold times. Also, if clocks change together, you'll miss a pulse.

I think this works. You may wish to take a few moments to verify it.

Regards, Bob Monsen

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C

Hi,



I've been trying to come up with a simple circuit to do the following: Accept 4 clock inputs and count the total number of pulses from each of the 4 clocks OR take the



4 clock inputs and output a single clock I can use with a regular counter.

I have 4 square wave clocks that I want to count. They vary from about 3 KHz to 40 KHz. This is what they look like (excuse my drawing skills).



Clock 1: ____----____----____ Clock 2: -____----____----____ Clock 3: --____----____----____ Clock 4: ---____----____----____



You get the idea. None of the rising or falling edges will ever interfere with each other. However, there are times when one or more clocks may be off (held low) like this:



Clock 1: ____----____----____ Clock 2: ___________________ Clock 3: --____----____----____ Clock 4: ---____----____----____



I want to end up with an accurate count of all the pulses from the 4 clocks. Does anyone have a simple solution to this? It's been driving me crazy but maybe I'm missing the obvious.



Thanks in advance.


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J

CLOCK1>---+-------------A | AND Y-----A +--[INVERT]---B OR Y------A +--B OR Y---> Output to counter CLOCK2>---+-------------A | +---B | AND Y--+ | +--[INVERT]---B | | CLOCK3>---+-------------A | | AND Y-----A | +--[INVERT]---B OR Y--+ +--B CLOCK4>---+-------------A | | AND Y--+ +--[INVERT]---B This circuit generates slivers equal to the propagation delays of the inverters at the outputs of the ANDs, so you may need to add a little delay to the inverters to make sure the slivers last long enough to make it through the ORs. Like this: CLOCKn>---+--------------------A | AND Y--- +--[INVERT]--[R]--+--B | [C] | GND A few microseconds should be plenty.
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J

--- Or, more simply:

CLOCK1>----[C]--+--[1N4148>]---+--->OUTPUT TO COUNTER |K | [1N4148] | | | GND | | CLOCK1>----[C]--+--[1N4148>]---+ |K | [1N4148] | | | GND | | CLOCK1>----[C]--+--[1N4148>]---+ |K | [1N4148] | | | GND | | CLOCK1>----[C]--+--[1N4148>]---+ |K | [1N4148] [R] | | GND GND

-- John Fields Professional Circuit Designer

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T

If you change those ORs to XORs it would at least reduce the chance of missing a pulse because it overlaps with the pulse from another AND.

I think the only way to do it seriously is to have 4 counters and add them. The Laws of Form could make a minimal solution with the same performance as

4 counters and adders, but it seems nobody ever figured out the Laws of Form. I will re-read the book some day. Maybe a light bulb will go on.
Reply in group, but if emailing add 2 more zeros and remove the obvious.
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