Determining a non-periodic digital timing scheme?

I have a piece of equipment (DLP projector) for which I am trying to construct a digital timing diagram. The digital signals this device uses are globally periodic (generally over several milliseconds) but aperiodic over a short time interval(ns to us). That is to say the waveform eventually repeats itself but is not repetitive over a short time interval. And so I can't get my scope (Tektronics) to produce a stable waveform for analysis. Taking a single time sequence is not particularly helpful as the record length of the scope is still only a fraction of the global period. Does anyone have any tips on how to deal with this problem? Thanks!

Reply to
JeffC
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Other than a storage scope? If you are just looking at timing, then a scope is overkill. You could store more information with a logic analyzer. I've worked at places (but haven't done this first hand) where the logic analyzer was used as a high speed frame buffer prior to analysis on a PC. We did that for flash data converters in the lab.

Reply to
miso

You want to readout the timing in detail ? Attach an FPGA and decode the signal to a parallel or logical form, then grab the parallel/logical stream.

Rene

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Reply to
Rene Tschaggelar

1) It's spelled Tektronix. It's a pet peeve of mine but has let me snag some cheap stuff on eBay. 2) You need a logic analyzer, sounds like a scope is just about the worst tool for what you want.
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Reply to
a7yvm109gf5d1

Thanks for all the replies. The INTRONIX LA1034 (pctestinstruments.com)looks ideal with the exception of the 2k sample limit which may be too short for my purposes.

Reply to
JeffC

You can buy real logic analyzers (old HP boxes) quite cheap if you don't need speed. Just make sure to get the pods with the analyzer. For instance:

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Those analyzers on ebay without pods are really boat anchors.

There may be more inputs than you need, so sometimes you can play games with external logic to increase the length of the sequence stored. For instance, you can build logic to store two samples, then feed them in parallel to the logic analyzer, effectively doubling the length of the sequence. When we were testing flash converters, the logic analyzer wasn't fast enough to process the data, but the data was paired two bytes at a time, then fed to 16 lines into the analyzer.

Reply to
miso

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