Designing MUX with tri sate bus in xilinx virtex II FPGA

Use 'Z's:

y=d0 when sel="00" else (others=>'Z'); y=d1 when sel="01" else (others=>'Z'); y=d2 when sel="10" else (others=>'Z'); y=d3 when sel="11" else (others=>'Z');

It can save timing, but only if the TBUFs are hand placed. In VirtexII, I think a carefully placed mux design will outperform the TBUFs, at least or reasonably sized muxes. Besides, the spacing of the TBUFs is not sufficient to connect up arithmetic that uses the carry chain.

Oleg wrote:

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

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"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

TBUFs are (were?) nice for the job where you had a batch of registers and a microcoded machine to read them onto a shared bus and load them from the bus.

Is there some obvious pattern to build a mux-equivalent that works well for reading one of 5 or 10 registers?

I'm thinking of something like a column would have an equivalent of the TBUF enable signal. Each bit slice would pass through the chain from the left and switch in its data bit if the TBUF was enabled. That switch could be an OR or MUX, whatever is easiest to implement. (It could even be an AND if you turn things upside down.) When you get to the end of the chain, you have the bus, and you turn it around and send it back to all the places that need to read it.

The obvious way uses 3 inputs on a LUT to make a 1 bit MUX. It seems as though there should be something better than using a whole column just to emulate a TBUF reading the adjacent register.

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759