Multi-channel ADC question

Without having checked your particular case, I would say this is not such a challenge nowadays. At 10 MSPS, 14 bit - moved as 16 bit words - I managed to do pump the data into a 100 MHz clocked

5420 DSP... this was 5 years ago. 30 KSPS is really slow, you should have plenty of options.

I know I am not giving you the soluton you are after but sometimes knowing that something has been done make things a lot easier...

Good luck,

Dimiter

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What ADC do you use?

Do you need to sample the signals at the exact same time or is multiplex still an option?

8 x 30k = 240k about half of the 500ksps your ADC is able to do. So you should still be able to use your ADC. The problem will be when you transfer the data from ADC to CPU if the bus is slow or the CPU is slow.

Some kind of FIFO between the ADC and the CPU will be a good thing.

If you instead use a DSP then you need to find a device that is fast enough to handle your data in realtime and create some kind of data pipeline that will never stall or else the constant flow of data through your system will stop.

Expensive solution with 8 discrete ADC but will also be a flexible solution. You will need to take of 8 data streams instead of only one multiplexed datastream.

Cheers Rune

The speed (in terms of pumping data into a DSP) is not a problem...the supplied serial ports have enough bandwidth for my application (16 bit

• 250 kSPS = 4 Mbit/s)

The biggest issues are

1) how to sample 8 channels with a minimum of external h/w and no downtime (i.e. switching between channels, switching/settling delay 2) If the processor has to control the switching lines, the processor may not be able to perform its intended task. DMA + offloading the switching to external circuitry seems like the best way to go, but I have no experience in the area. I was wondering if anyone has encountered this.

I agree, this is *not* a crazy high-end application. Someone must have ventured down this path before! :)

You will probably indeed have to use DMA, sampling for DSP purposes tends to be continuous so this will make things simpler. Also, the DSP architectures I know, have DMA channels dedicated to the respective serial or whatever ports, so this will take no extra effort on your behalf.

Sampling is a totally different issue. If you want to sample a waveform with 16-bit precision at 30 kSPS, you will have to make sure the jitter is low enough. This may take doing some more reading and/or some maths. You may be able to use the DSP serial port sync signal to clock the sampling, multiplexing the channes may also be clocked by it (say, some external counter or something). Arranging the data inside the DSP memory may be less of an issue than you probably expect, have a look at the serial ports with DMA on the 54XX DSPs of TI or the like, you'll be surprised at the level of flexibility they offer.

Dimiter

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You can auto jump to next channel of some of the ADCs.

Depending of your sampling frequency you can for example use a crystal osc with some kind of temp compensation to increase precision and divide the clock rate to "channels" x "samples per second". You will need an ADC with external sampling trigger.

Not the correct ADC but just as an example you could look at AD7928 from analog.com. The ADC has a sequencer that auto switch to next channel after each conversion, a trigger input that can be used to start the sampling process from an external clock system and a serial interface that can stream the data to a serial port of differents kind of microcontrollers.

Cheers Rune

FPGA

Mid range FPGA should work, with at least 256 balls (they don't come in pins).

If you intend to use a fast ADC with a multiplexer in front of it, you must put analog anti-alias filters in front of every input channel of the mux.

It might be easier to use separate delta-sigma converters for each channel, which have inherent anti-aliasing.

If accurate DC levels or frequency response down to DC is _not_ required, then it might even be possible to use audio ADCs, with 2-6 ADCs on a chip. Unfortunately, it seems to be hard to get any worst case specs for these devices.

Paul

Hello Dave,

That is usually done by using a sample and hold (S&H) for each channel. You sample all of them at the same time, thus eliminating the delay issue. Then the ADC input multiplexer trundles from one S&H to the next. Typically the storage element is a capacitor.

I am sure there are plenty of chips to do that but you'd have to scope the market for that. I always did mine discrete or using chips for the switches such as the SD5400. That one became a bit expensive so now I prefer discrete FETs, maybe you can get away with a couple of 4066 chips.

Just one word of caution: If you decide to roll your own make sure the capacitors are 'the good stuff'. Cheap ceramic capacitors aren't too great if you need 16 bit accuracy. And mind the input impedance (and capacitance) of your ADC.

Regards, Joerg

Dave,

As Linnix said in his reply, withough knowing more details of your requirements this sounds an ideal application for an FPGA.

I've been using a 1Msps 12 bit ADC with a serial interface (AD7495). I haven't checked but I'd suspect there are similar/cheaper devices that will do 14 bits at 30KHz.

An FPGA can drive these in parallel and present the interleaved results for your uP to read.

You might even get away with a large CPLD.

I don't know why Linnix says FPGAs don't come in packages with pins, all the low end devices of the sort you need have QFP packages available.

Hope this helps,

Nial

------------------------------------------------------------- Nial Stewart Developments Ltd FPGA and High Speed Digital Design

I agree the FPGA or CPLD will do the job, however I would not be that hasty to design in one. Serially interfaced ADCs are commodity nowadays and many MCUs and DSPs have convenient direct interfaces to them (e.g. I just designed in the AD7495 in an MPC5200 based system, it just takes the wires to conect; and you can connect a number of those).

It is all down to the application, of course, it still may be that the FPGA or CPLD is the best choice.

Dimiter

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You're right Dimiter, if the pins are available a direct interface to 8 converters might be simpler.

My problem is I've been doing FPGA based design work for about

10 years now, and as someone said "when your only (usual) tool is a hammer, everything looks like a nail!"

Nial.

------------------------------------------------------------- Nial Stewart Developments Ltd FPGA and High Speed Digital Design