Hello, Does anybody know a simple way to get the following clock signals. Ideally it would be a single device as below:
Input1: F Mhz differential, can be LVDS/ LVPECL. F ~ 300-350 Mhz. Output1: F Mhz LVDS fixed Output2: F Mhz OR F/2 Mhz LVPECL, selectable by pin setting.
Desirable: 2:1 input mux also available with the device
The closest I have got is to use Onsemi LVEL37 to do fixed divide by 1 and divide by 2 at LVPECL levels, and then generate Output1 with an LVDS translator and Output2 thru a 2:1 PECL mux (EL57).
The LVEL37 does also provide the 2:1 input mux.
The Maxim MAX9377/9378 devices would really have fitted if they were pin-selectable divide by two instead of divide by four.
Thanks for any tips, Jai Warrier ADS Networks
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