I need to delay one of the output signals from my cpld by 80nS. The clock frequency of our board is 48MHz.
Im using the altera quartus software.
We have data and address lines and a chip select going into the cpld. The outputs are open drain. When the data and address lines are changed from a Low to a High state they take about 60ns to rise up on the ouputs of the CPLD.
The problem is the chip select line is active low and drops from a high to a low almost instantaneous. So things aren't lining up.
I was able to move the chip select drop to a low by adding in LCELL's. This delayed the chip select until the data and address lines are set up on the outputs.
The problem now is that the chip select line is now moved along and does not return high before the data and address lines change.
i am trying to set the chip select back high after a set amount of time but the software does not seem to be registering the TIMING in the VHDL code.
For example, in my open drain code i am trying to reset the output of the chip select high but it is not happening.
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