Hi, I'm discovering the wonderful world of FPGA, so please excuse the probably stupid question and use of improper terminology.

It seems to be a trivial case of the difficult "state assignment problem" but i must admit i'm to lazy to read the 199 pages of

There are 2 very simple situations in FSM

- n-step cycle S1 -> S2 -> Sn -> S1 -> S2 -> ....
- n-step, last is a sink : S1 -> S2 -> Sn -> Sn -> Sn -> Sn ... that can be easily implemented with counters, binary, gray code, whatever.

The question is: what's your favorite representation when you have strong restrictions on the number of gates/FF ?

I guess everybody uses a standard binary counter for large values, say N>1000) with initial state = 0 and last = N-1, or the other way, but are there "good practices" for small ones ?

Michel Billaud