I'm trying to understand the intricacies of implementing a ROM in an FPGA. I've searched around and come up with some useful tidbits, but I was hoping someone here could clear up a few issues with doing it "right" for those looking to learn. I would greatly appreciate any comments on the "correctness" of the following (using VHDL):
- There seem to be two common ways to do the implementation: one is to create an array and essentially index into it using a mux, the other seems to involve generating RAM with predefined values and then defining it as read-only. The latter seems to be preferred for large LUTs (why?).
-- On that note, is there a preferred template for doing the latter? I know what a RAM template looks like, how does one go about forcing it to predefined values and setting it to read only? (or is it just a matter of directing the RAM input/enable ports nowhere)
-- Also, I notice Altera has a ROM megafunction, am I restricted (at least in terms of ease of creation) to the altera megafunction or is it relatively easy to roll my own RAM based ROM?
- Are there any particular considerations if I am looking for a dual ported ROM? (except for the fact that the megafunction doesn't seem to support dual ports)
- What about initialization? Right now I have a Matlab file that spits out text that is formatted such that I can cut and paste. Is there an easier way with the VHDL file read functions, that still remains synthesizable? Any considerations in this regard for RAM based versus mux based?
For the curious, I'm trying my hand at direct digital synthesis: this is a 1/2 wave LUT (the other half is just the negative of the first, done on the fly, I haven't tried to reduce this to 1/4 yet). The dual ports stem from the need to access the sine and cos portion (phase and phase-(1/4 wave length) index).
I realize this topic roughly comes up in one form or another every now and then, but I am trying to put the knowledge in one place and figure out how to do it "right" for the sake of learning.