Hi,
I am developing evaluation board using samsung s3c2410 (Arm920T core chip. It is connected DSP which sends interrupt with 0.9ms period to le arm9 check data updates (with 1ms period)in the DSP internal registers. (that means register update and interrupt is asynchronous each other).
It had worked well before (it is compiled using ads c++ compiler). However... It has started losing the updated register (sometimes) after I had adde new task which needs heavy computational loads. In my thought there can b interrupt latency due to the new task.
I guess the size of I-cache can be problem. the size of compiled binar file including the task only is about 60Kb.
the new code took 40 ms to finish and it's loads are just 4 % of overal system (new task's deadline period is one sec and MPLL of arm9 is 20 MHz). Do you think the increase of miss rate of I-cache can be the reason? or are there another problem which increase interrupt latency?
And If I use cache locking, how much speed would I lose?
Thank you for reading...
dungglee.
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