Hi newsgroup,
As shown in the VHDL code I am feeding two flip flop chains with the same input. The chains use complementary clocks (200Mhz).
In the process "rise_fall" I do some combinational logic to detect rising and falling of the sampled input.
Now I want to use one of the combinational signals as a clock in a process "clksel" to sample the second combinationl signal.
Speaking in terms of functional simulation the function of the hardware description is the following: The signal which gets active first is used for ClockSel.
The output ClockSel is then used to feed a DCS module.
The problem I see in this hardware description is that the clock in the process "clksel" is a gated clock.
What is your opinion about the desription ? How can I modify it to make it synthesizable ? Is there some need for additional constraints ?
library ieee; use ieee.std_logic_1164.all;
entity ana is port( Reset : in std_logic; Clk : in std_logic; DataIn : in std_logic; ClockSel : out std_logic ); end ana;
architecture arch_ana of ana is
signal r_p1, r_p2, r_p3 : std_logic; signal f_p1, r_p2, r_p3 : std_logic;
signal trig_rise, trig_fall : std_logic;
begin
------------------------------------ sync_redge: process(Reset, Clk) begin if Reset='1' then r_p1