Hi all,
I am having some problems when reconfiguring a Virtex FPGA using JBits.
BRAMs have a registered output and, after a partial reconfiguration, this register is reset and the behaviour of the design for one cycle is not the expected.
The output from the BRAM was supposed to be 0 1 2 3 4 5 6 7 8 9 And I get 0 1 2 3 4 (reconfiguration) 0 6 7 8 9
Do you know how can solve this problem? Of course, I can change the BRAm for a distributed RAM, but this is not a valid solution for my case.
Best regards, David de Andrés