Hi folks,
I'm working on developing an embedded system with a xilinx v2pro fpga. I have all my code for the ppc (including 2 block rams, one on the plb and the other on the opb) done in xps, and exported it to the project navigator. I am trying to add an additional block rom, but I don't want to add it in the EDK, I just want it to communicate directly with fpga fabric. So, I used the core generator, and created a bram instance that is 70 bits wide, and 8k deep. The core generator doesn't create a .bmm or .mem file to accompany this. So how do I go about adding the proper lines to the current bmm file? I haven't found much for documentation on this. If I don't add any information for the new ram to the bmm file created by xps, then when I import the projnav files back into xps, and regenerate the bitstream, data2mem errors out on me. Currently, my bmm file looks like this: ADDRESS_BLOCK plb_bram_if_cntlr_1_bram RAMB16 [0xffffc000:0xffffffff] BUS_BLOCK top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_0 [63:56] ; top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_1 [55:48] ; top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_2 [47:40] ; top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_3 [39:32] ; top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_4 [31:24] ; top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_5 [23:16] ; top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_6 [15:8] ; top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_7 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK; ADDRESS_BLOCK opb_bram_if_cntlr_1_bram RAMB16 [0x00000000:0x00003fff] BUS_BLOCK top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0 [31:28] ; top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_1 [27:24] ; top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_2 [23:20] ; top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_3 [19:16] ; top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_4 [15:12] ; top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_5 [11:8] ; top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_6 [7:4] ; top/opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_7 [3:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK;
I'm not entirely sure how the rom needs to get assigned in the fpga. I was thinking of adding a line such as: ADDRESS BLOCK pattern_rom RAMB16 [0x00040000:0x00042000] END_ADDRESS_BLOCK; (where "pattern_rom" is my rom I added in the fpga from the coregen) But, I'm not sure how to complete the BUS_BLOCK section.
Any help would be appreciated!
Thanks,
-- Matt snipped-for-privacy@iol.unh.edu