Block Ram clocks

I'm using block rams to create FIFOs in Virtex II device.And mapper report problem with using clock, that drives these block rams:

WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX symbol "clock_reset_clk80_bufg" (output signal=clk) has a mix of clock and non-clock loads. Some of the non-clock loads are (maximum of 5 listed): Pin CLKA of txfifo1_bram3 Pin CLKB of txfifo1_bram3 Pin CLKA of txfifo1_bram2 Pin CLKB of txfifo1_bram2 Pin CLKA of txfifo1_bram1

I'm a little suprised, because I thought that these ARE clock loads. Should I worry about that? Any other comments?

-- Robert Pudlik