Hi everbody,
The Stratix PCI kit is a 32/64-bits PCI board from Altera with 256 MB of DDR SDRAM (SO-DIMM). This kit includes a nice reference design that has a PCI to DDR bridge. We would like to use this design as a starting point for our own designs.
Unfortunately this design only works with the old Quartus II v2.1 and the v1.2.1 SDRAM IP Megacore from Altera.
Importing the older project in the newer Quartus 4.2 does not work. We tried creating a new project with the cores, pin settings, constraints etc. But the only thing that can be read from the DDR memory is garbage. Worse, it even gives this garbage when the SO-DIMM module isn't even inserted (it reads out: 9d66001b .... 9d22001b, while the working design gives something like ffff00 in that case (which is far more logical for disconnected hardware IMHO).
We tested this with both the old and the new SDRAM Megacore. Could this be some project setting we overlooked? Byte lanes? Assignments? LogicLock settings?
I tried asking Altera for help, they suggested downloading a newer PCI core because it included a newer reference design. Unfortunately that one doesn't use DDR but SDR instead. Then I asked if they could send me a reference design from one the newer kits (hoping to extract some useful information from it), and they said they can't (???).
It probably has something to do with the datapath, because the system reads out garbage from the 'memory' even when the module isn't psysically present in the system. Though, I don't understand why...
Anybody had any luck converting the (kit included) PCI 2 DDR reference design (Quartus II 2.1) to the new Quartus 4.2?
Have a nice day!
-- Edwin