I have a customer who builds single-pixel cameras based on compressive scanning (basically using 2-D Walsh functions as spatial filters and combining the results using black magic). This is a big win in wavelength ranges for which good cheap area arrays don't exist.
I'm designing them a front end board that has a whole lot of medium-speed bootstrapped TIAs, for an infrared camera, so I'm facing the usual ten-pounds-in-a-five-pound-bag problem--TSSOPs, SC75s, 0201 resistors. (Sumdimes ya godda do wudya godda do, as they say in Brooklyn.)
Is there a decent quantitative way to estimate the required area for this sort of nonsense^H^H^H^H^H^H^H^H technology?
Thanks
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot net
http://electrooptical.net
The old parts-per-square-inch metrics are very useful any more. Lost of experience with similar parts can train your guesstimate ability pretty well. But the best thing to do is hack a schematic, import into your PCB program, and push stuff around. Iterate on that.
Things like connectors and mounting holes can be real area-gobblers.
--
John Larkin, President Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators
If it's dozens of repeated stages you could place one and try to squish it into a desirable form factor. That's how it's done on IC designs and sometimes on a board.
Another option since you use Eagle: There is some sort of auto-place ULP but I've never used it myself. It can do some of the squishing for you. Mightb be worth a look, or if necessary a post in a Cadsoft NG (they have Englisch ones).
If it still don't woik, as they say in Noo Yoik, consider 01005 parts and maybe flip-chip bonded die for the ICs. The datasheets and distributor lists may not show the die, you'd have to call the manufacturers on availability, pricing and MOQs.
Thanks. If these folks get to the point where their volumes can support that, I'll strongly recommend doing a laser-trimmed hybrid. Almost half the board complexity is due to servoing out the offset of the bootstraps, but their drift is low enough that getting rid of unit-to-unit variations would be enough.
If it really won't fit, we may just buy a few reels of parts at once, and figure out the right resistor value for the batch--the poor man's version of laser trimming. We'd get about 100 cameras per reel, so at this stage that would probably be OK, if not absolutely optimal.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot net
http://electrooptical.net
Might want to check IC design houses for massively integrated multi-channel amps, for ultrasound and similar apps. That's a lot of legwork though. You could also consider hybrids where resistors can actually be underneath other parts because they are deposited.
And then there's always real IC design. I am sometimes involved in projects where there's dozens to over 100 channels per die.
But I bet as the master of ceremonies you are the ione who has to see it through to successful completion :-)
There is always hope :-)
Unfortunately, the smaller the real estate available the more expensive that hope gets. An IC design can easily swallow half a million just in NRE.
You could also consider a normal (non-alumina) board and active laser-trimming of SMT resistors. Best to talk with Vishay or another resistor manufacturer about that. I haven't seen it for smaller sizes than 0402 which is like a boulder in your case but maybe it can be done.
I read an article, yesterday I think, where TI was now offering bare die in small qty, even as low as 10 for prototyping. I do not remember what products are being offered. I think some of the analog products, MCUs and DSPs.
Larkin's First Law: Generalizations don't mean much.
--
John Larkin, President
Highland Technology, Inc
jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro acquisition and simulation
Wow, self referential and self-refuting on the first try. Are you a Zeno on your mother's side? ;)
Don't worry, physicists make even worse philosophers than EEs do, but fortunately nowhere near as bad as biologists.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot net
http://electrooptical.net
The rule that was used at the last place I worked at that really needed to squish boards down was that the board area used needed to be about twice area of the total combined areas of the components. That's for multi-layer boards where the top (and bottom, if you populate it) can just be used for components and vias down into the interior.
If you use the bottom of the board for components you can count its area, but you have to remember that anything that's through-hole uses up space twice. And you have to figure on using lots of interior layers, and needing a really good layout guy.
The fly in the ointment here is that the rule was developed empirically, by a group that abhorred designing with transistors -- and the actual occupied footprint of a transistor or a passive is a greater proportional increase over the component area itself than what you'd see in a honkin' big microprocessor or FPGA. So I'm not sure how it'd fly for you.
I'd be inclined to do one of the following:
1: use the occupied component footprint, with the above rule. By occupied footprint, I mean look at the actual footprint on the board for the component and it's pads, draw a square around it, and use that area.
2: Use the occupied footprint of each component plus vias for each lead (that presumably take the traces down to middle layers), plus half the inter-component clearance that you're going to design for. In other words, for each package place the footprint and one via per lead, rubber- band a rectangle around it with due consideration for clearance, and use the area of that rectangle. Then add everything up, and plan on needing something like 125% to 150% of that much area for real. (Don't forget mounting holes, connectors and the like).
3: Combine either 1 or 2 with Jeorg's suggestion to Really Flog the placement on one of those 32 circuits, then use that area times 32 (assuming that the tile will fit well on the board) to decide how much area you have left for all the other inevitable folderol.
--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
I usually get all the major components on a board and play around. In many cases what seems hopeless to begin with works out just fine. The biggest problems are holes and components with a fixed location like connectors and big components that are in the way of other mechanical stuff. Like John I have my own rule. Nico's rule says there is room for N+1. In short the 'N+1 rule' :-)
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------
That's pretty much the rule-of-thumb I used for I/C layout back at the beginning of time... Connect-up area equal to active area.
Now I figure only about 20% of active area for connect-up since I almost always have 5 layers of metalization.
Anytime I start using a new process, I study the layout rules, and write an "area template" for each component type... a template that scales with parameters such as L, W, NF, etc.
When I'm done with a design, I "netlist" it using the area template. Then an executable (written by son, Aaron, natch ;-) computes the estimated active chip area, something that would be impossible to do by hand (a task much like taking the census, with only one person doing the job :-)
You could probably do the same for a PCB, but it would be more difficult, requiring an "area library" with every part you plan to use. But maybe not so insurmountable... you do have a footprint library. Maybe someone could write an executable that would use information from the footprint library??? I don't know.
...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Old man Muntz would have said "You are wasting real estate". When I did my first hybrid in 1986/87 the CAD kept beeping all the time. Interference, interference, gaaaaah. So we'd had it with the CAD, took scissors, cut out parts in 20x size or so and shoved them around a glass plate until we had a super tight fit. Interleaving SOT parts and all that. The boss came buy. "Dude, what's with all these paper snippers? This ain't kindergarden here".
WHAT? We got only four. How did you do that? Redeem some chip miles for an extra layer?
That's how I did my original OpAmp (MC1530)... paper dollies on a quadrille pad, see page 6...
formatting link
SilTerra Process CMOS13H32. Also a "heavy" metal upon request, for high currents.
I think there are even some six and seven layer processes available out there. ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
IBM processors were made with 10 or 11 levels at the time I left (2009).
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot net
http://electrooptical.net
Awwww, and I thought we'd see the paper dollies. I kept my paper-hybrid for years. But then the paper elements and most of all the tape started curling up and its time had come. Should have taken a photo.
We also have one "heavy metal".
Can't have it. We are on the XH-035 with high voltage extension.
Do mean 10-11 "stack" (process) levels, or 10-11 metalization layers? My last IBM library usage was "IBM6HP", which, IIRC, had 4-layers of metal... or 5-layers if you used the MiM capacitor. ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
11 metals. I have a cross-section photo in some presentation someplace. IIRC it was three plated-up fatwire levels on the top, then progressively finer stuff down to the gate level.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot net
http://electrooptical.net
I've used that also. XFAB is my favorite process house. Nice bunch of people to work with. ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
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