Hi I would like to know if any of you knows a good paper (app note etc.) that describes the xilinx slice sturcture in details, I know the general cell architecture (e.g. - two LUTs, Two regs and carry logic) but I wanted to get a lot more fimiliar with the architecture and functionally of each logic element in the cell, for example how exactly does the carry logic is structured etc.
The reason for this qeustion is that I want to implement arithmetic block using as less logic and routing as possible I wonder if there is an application note that explains how to code and route your arithmetic functions in a way that is best suitable for the xilinx chip (spartan 2E).
So if any of any of you is fimiliar with such a paper I will be grateful for a link.
Regards MC