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Silicon area

I'm trying to work out how silicon area in power trs and ICs relates to both current and power ratings, and how device cost relates to both silicon area and package type. So I'd like to get a clearer idea of what tradeoffs I can make to reduce costs, via both changing silicon area and package type. For example if I were to double current handling requirement while halving power handling requirement, resulting in a lower Pdiss package, I'm looking to understand better what effect this would have on total cost.

I don't see a ready way to deduce all this by looking at prices of individual trs on the market, as they vary too much in other ways, other specs, supply v demand, varying sources with different pricing etc.

NT

Reply to
NT
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"Nutcase Troll

** Just supply all yout transistors with 1 amp of base current.

Problem solved .....

( Wot a f****it )

... Phil

Reply to
Phil Allison

An application-specific spreadsheet sometimes will give you an idea on cost trade-offs. It will only be useful that one time - and you'll have to do all the figgering yourself, as your own purchasing and supply situation is likely unique.

Start simple, with just one component location, in one schematic of one project. Rules of thumb in pricing seldom last longer than six months, so get the project out the door. Your own time spent dithering can end up being the biggest expense involved.

RL

Reply to
legg

For small signal transistors, the major costs are the package and then testing; the silicon is not relevant regarding pricing. For power transistors, the die must get in the region of a square inch or more to become a cost factor..

Reply to
Robert Baer

"Robert Baer"

** Automated testing of small signal BJTs takes only milliseconds.
** Funny how I cannot buy a BUZ905D in Sydney for less than $40 apiece.

It's a dual chip, lateral MOSFET in TO3 pack.

Each chip is about 7mm square.

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.... Phil

Reply to
Phil Allison

  • Yes, _test_ time is in the millisecond region but the (automated) handling (time and equipment) along with cost of testing exceeds the cost of the die; many thousands per wafer with near 100 percent yield.
  • That is what they feel they can charge for it; it does not matter if the finished part costs around 40 cents to make..
Reply to
Robert Baer

Thank you, so it sounds like its alll about Pdiss, and making a circuit config choice that halves Pdiss while increasing Ic will be a winner.

cheers, NT

Reply to
NT

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