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Speed vs Area Optimisation

Hi! I'm a newbie at designing circuits on FPGA and I have found out something I cannot understand very well. I've written the VHDL description of some Linear Feedback Shift Registers and I have synthesised them with Xilinx's xst using different optimisations: for Speed and for Area. I've noticed that, even if the Speed optimisation leads in many cases to a faster circuit, sometimes it produces a slower circuit than the Area optimisation. Though, this is quite infrequent. The real problem, is with the Area optimisation, that, according to xst's Synthesis Report, often produces a circuit with more flipflops, used slices, and bonded IOBs than Speed optimisation. The only unchanged or lower values are the number of BELs and LUTs used. How can this be? Am I looking at the wrong values to see whether the area has been reduced or not? Or is it a problem with some XST parameter? Thanks in advance to everyone who will answer! FlyingPenguin

Reply to
FlyingPenguin
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This is a gray area. Maybe some otherwise unused flops were called up to save some more valuable LUTs.

Area/Speed settings are hints rather than constraints and as you have seen, they don't always work.

I have found that the effect of changing this setting is small and the the default AUTO setting is as good as any on the average.

-- Mike Treseler

Reply to
Mike Treseler

It actually isn't unusual for optimizing area to produce slightly better timing figures. The router is trying to shrink the amount of space the design uses, so the timing *can* improve due to shorter routes between signals. On the other hand, it may also result in worse timing. However, as Mike pointed out, you don't get much more than just using auto.

In general, you only need to mess with those settings when your design either doesn't make timing by a small margin, or won't fit by a small margin. Sometimes, you can get the design to make timing, or fit, with a little extra effort, and that's what those settings do - they tell the software to push a little harder in one direction or the other.

If you are comfortably making timing, and easily fit in your target device, you shouldn't see much difference at all.

Reply to
radarman

Actually, I have no target device at all. I just had to synthesise those components using many different devices and settings, and gather all the data. I had some trouble interpreting them, but your and Mike's answers are exactly what I was looking for.

Thanks!

FlyingPenguin

Reply to
FlyingPenguin

FlyingPenguin schrieb:

The number of used slices is irrelevant. The circuit is mostly implemented by LUTs. Two LUTs can be placed in the same slice (1 slice used) or in two different slices (2 slices used) for the same circuit. As your FPGA gets more and more crowded more and more slices will have two used LUTs.

In an extreme case, you can have a circuit that uses 98% of slices but only 49% of LUTs. Two of these circuits will fit in the same FPGA.

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DFF usage is irrelevant as long as there are less DFFs than LUTs.

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Bottom line: Count LUTS.

Kolja Sulimma

Reply to
Kolja Sulimma

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