Hi,
Can anyone suggest how to assign a area constraint on a sub-module within my design? I dont care where the other sub-modules are as long as this particular sub-module is in the required area. I know we can assign a area constraint for the whole design. But, how to do it for a sub-module?
Thanks in advance, Ramtilak
For Xilinx FPGA and tools, add something like below to the ucf file:
INST ?hierarchy/path/to/submodule? AREA_GROUP = "your_area_group_name"; AREA_GROUP ?your_area_group_name? RANGE = range;
HTH, Jim ( snipped-for-privacy@yahoo.com remve NOOOSPAM)
remember to check the KEEP_HIERARCHY in the XST Options, and put AREA_GROUP ?your_area_group_name? PLACE = CLOSED; AREA_GROUP ?your_area_group_name? GROUP = CLOSED;
Kelvin
or you could use the incremental design flow
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