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How do I put LOC constraint on a coregen DPRAM?

Hi, group:

I am running core generator to make some dual port RAMs. However my design involves partial reconfiguration, I need to put some LOC constraint on the instantiated DPRAMs, or at least find a way to confine the instance within an area group of their instantiator...How may I do that?

Kelvin

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kelvin8157
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BTW, I am using Virtex-2 3000...and ISE6.1...

Thanks. Kelvin

group

Reply to
kelvin8157

Kelvin, Use the floorplanner to find the name of your blockram after the translate stage. Then add a LOC constraint in your UCF file. Read the 'Xilinx constraints guide' to find out about the syntax, something like INST "RTFM_BRAM" LOC = X0Y0; HTH, Syms.

Reply to
Symon

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